/**
 *******************************************************************************
 * @file  hc32f160_interrupts.h
 * @brief This file contains all the functions prototypes of the interrupt driver
 *        library.
 @verbatim
   Change Logs:
   Date             Author          Notes
   2020-11-27       CDT             First version
 @endverbatim
 *******************************************************************************
 * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
 *
 * This software component is licensed by HDSC under BSD 3-Clause license
 * (the "License"); You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                    opensource.org/licenses/BSD-3-Clause
 *
 *******************************************************************************
 */
#ifndef __HC32F160_INTERRUPTS_H__
#define __HC32F160_INTERRUPTS_H__

/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif

/*******************************************************************************
 * Include files
 ******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"

/**
 * @addtogroup HC32F160_DDL_Driver
 * @{
 */

/**
 * @addtogroup DDL_INTERRUPTS
 * @{
 */

#if (DDL_INTERRUPTS_ENABLE == DDL_ON) || (DDL_EXTINT_NMI_ENABLE == DDL_ON) ||   \
    (DDL_EKEY_ENABLE == DDL_ON)

/*******************************************************************************
 * Global type definitions ('typedef')
 ******************************************************************************/
/**
 * @defgroup INTC_Global_Types INTC Global Types
 * @{
 */
/**
 * @brief  Interrupt registration structure definition
 */
typedef struct
{
    en_int_src_t    enIntSrc;   /*!< Peripheral interrupt number,
                                     can be any value except INT_PORT_EIRQ0~7 @ref en_int_src_t         */
    IRQn_Type       enIRQn;     /*!< Peripheral IRQ type, can be Int008_IRQn~Int023_IRQn @ref IRQn_Type */
    func_ptr_t      pfnCallback;/*!< Callback function for corresponding peripheral IRQ                 */
}stc_irq_signin_config_t;

/**
 * @brief  NMI initialize configuration structure definition
 */
typedef struct
{
    uint32_t    u32NmiSrc;      /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details                */
    func_ptr_t  pfnNmiCallback; /*!< NMI Callback function pointers                                         */
}stc_nmi_init_t;

/**
 * @brief  EXTINT initialize configuration structure definition
 */
typedef struct
{
    uint32_t    u32ExtIntFilter;        /*!< ExtInt filter clock, @ref EXTINT_FilterClock_Sel for details         */
    uint32_t    u32ExtIntFilterClock;   /*!< ExtInt filter clock division, @ref EXTINT_FilterClock_Div for details*/
    uint32_t    u32ExtIntLevel;         /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details            */
}stc_extint_init_t;

/**
 * @}
 */

/*******************************************************************************
 * Global pre-processor symbols/macros ('#define')
 ******************************************************************************/
/**
 * @defgroup INTC_Global_Macros INTC Global Macros
 * @{
 */
/**
 * @defgroup INTC_DefaultPriority_Sel Interrupt default priority level
 * Possible values are 0 (high priority) to 3 (low priority)
 * @{
 */
#define DDL_IRQ_PRI_DEFAULT         (3U)
/**
 * @}
 */

/**
 * @defgroup INTC_Priority_Sel Interrupt priority level 00 ~ 03
 * @{
 */
#define DDL_IRQ_PRI00               (0U)
#define DDL_IRQ_PRI01               (1U)
#define DDL_IRQ_PRI02               (2U)
#define DDL_IRQ_PRI03               (3U)
/**
 * @}
 */

/**
 * @defgroup INTC_Register_Protect INTC Registers Protect Code
 * @{
 */
#define INTC_REG_UNPROTECT          (0xA5U)
#define INTC_REG_PROTECT            (0x00U)
/**
 * @}
 */

/**
 * @defgroup NMI_TriggerSrc_Sel NMI trigger source selection
 * @{
 */
#define NMI_SRC_XTAL_STOP           (INTC_NMIER_XTALSTPEN)
#define NMI_SRC_SWDT                (INTC_NMIER_SWDTEN)
#define NMI_SRC_LVD                 (INTC_NMIER_PVDEN)
#define NMI_SRC_MASK                (NMI_SRC_XTAL_STOP | NMI_SRC_SWDT |         \
                                    NMI_SRC_LVD)
/**
 * @}
 */

/**
 * @defgroup MNI_Register_Msk NMI register mask
 * @{
 */
#define INTC_NMIER_MASK             (INTC_NMIER_XTALSTPEN   |                   \
                                    INTC_NMIER_SWDTEN       | INTC_NMIER_PVDEN)
#define INTC_NMIFR_MASK             (INTC_NMIFR_XTALSTPF    |                   \
                                    INTC_NMIFR_SWDTF        | INTC_NMIFR_PVDF)
#define INTC_NMICLR_MASK            (INTC_NMICLR_XTALSTPCL  |                   \
                                    INTC_NMICLR_SWDTCL      | INTC_NMICLR_PVDCL)
/**
 * @}
 */

/**
 * @defgroup EXTINT_Channel_Sel External interrupt channel selection
 * @{
 */
#define EXTINT_CH00                 (1UL << 0U)
#define EXTINT_CH01                 (1UL << 1U)
#define EXTINT_CH02                 (1UL << 2U)
#define EXTINT_CH03                 (1UL << 3U)
#define EXTINT_CH04                 (1UL << 4U)
#define EXTINT_CH05                 (1UL << 5U)
#define EXTINT_CH06                 (1UL << 6U)
#define EXTINT_CH07                 (1UL << 7U)
#define EXTINT_CH08                 (1UL << 8U)
#define EXTINT_CH09                 (1UL << 9U)
#define EXTINT_CH10                 (1UL << 10U)
#define EXTINT_CH11                 (1UL << 11U)
#define EXTINT_CH_MASK              (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 |  \
                                     EXTINT_CH03 | EXTINT_CH04 | EXTINT_CH05 |  \
                                     EXTINT_CH06 | EXTINT_CH07 | EXTINT_CH08 |  \
                                     EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11)
/**
 * @}
 */

/**
 * @defgroup EXTINT_FilterClock_Sel External interrupt filter function selection
 * @{
 */
#define EXTINT_FILTER_OFF           (0U)
#define EXTINT_FILTER_ON            (INTC_EIRQCR_EIRQFEN)
/**
 * @}
 */

/**
 * @defgroup EXTINT_FilterClock_Div External interrupt filtersampling  clock division selection
 * @{
 */
#define EXTINT_FILTER_CLK_DIV1      (0U)
#define EXTINT_FILTER_CLK_DIV8      (INTC_EIRQCR_EIRQFCLK_0)
#define EXTINT_FILTER_CLK_DIV32     (INTC_EIRQCR_EIRQFCLK_1)
#define EXTINT_FILTER_CLK_DIV64     (INTC_EIRQCR_EIRQFCLK)
/**
 * @}
 */

/**
 * @defgroup EXTINT_Trigger_Sel External interrupt trigger method selection
 * @{
 */
#define EXTINT_TRIG_LOW             (0U)
#define EXTINT_TRIG_RISING          (INTC_EIRQCR_EIRQTRG_0)
#define EXTINT_TRIG_FALLING         (INTC_EIRQCR_EIRQTRG_1)
#define EXTINT_TRIG_BOTH            (INTC_EIRQCR_EIRQTRG)
/**
 * @}
 */

/**
 * @defgroup EXTINT_Register_Msk EXTINT register mask
 * @{
 */
#define INTC_EIRQF_MASK             (INTC_EIRQFR_EIRQF)
#define INTC_EIRQCLR_MASK           (INTC_EIRQCLR_EIRQCL)
/**
 * @}
 */

/**
 * @defgroup INTC_EKEY_Channel INTC EKEY channel selection
 * @{
 */
#define EKEY_CH00                   (uint8_t)(1U << INTC_EKEYCR_EKEY0EN_POS)
#define EKEY_CH01                   (uint8_t)(1U << INTC_EKEYCR_EKEY1EN_POS)
#define EKEY_CH02                   (uint8_t)(1U << INTC_EKEYCR_EKEY2EN_POS)
#define EKEY_CH03                   (uint8_t)(1U << INTC_EKEYCR_EKEY3EN_POS)
#define EKEY_CH04                   (uint8_t)(1U << INTC_EKEYCR_EKEY4EN_POS)
#define EKEY_CH05                   (uint8_t)(1U << INTC_EKEYCR_EKEY5EN_POS)
#define EKEY_CH06                   (uint8_t)(1U << INTC_EKEYCR_EKEY6EN_POS)
#define EKEY_CH07                   (uint8_t)(1U << INTC_EKEYCR_EKEY7EN_POS)
#define EKEY_CH_MASK                (EKEY_CH00 | EKEY_CH01 | EKEY_CH02 |        \
                                     EKEY_CH03 | EKEY_CH04 | EKEY_CH05 |        \
                                     EKEY_CH06 | EKEY_CH07)
/**
 * @}
 */

/**
 * @}
 */

/*******************************************************************************
 * Global variable definitions ('extern')
 ******************************************************************************/

/*******************************************************************************
  Global function prototypes (definition in C source)
 ******************************************************************************/
/**
 * @addtogroup INTC_Global_Functions
 * @{
 */

/**
 * @brief  AOS software trigger.
 * @param  None
 * @retval None
 */
__STATIC_INLINE void AOS_SW_Trigger(void)
{
    WRITE_REG32(bCM_AOS->INTC_STRGCR_b.STRG, Set);
}

/**
 * @brief  INTC lock, register write disable
 * @param  None
 * @retval None
 */
__STATIC_INLINE void INTC_Lock(void)
{
    WRITE_REG32(CM_INTC->FPRCR, INTC_REG_PROTECT);
}

/**
 * @brief  INTC unlock, register write enable
 * @param  None
 * @retval None
 */
__STATIC_INLINE void INTC_Unlock(void)
{
    WRITE_REG32(CM_INTC->FPRCR, INTC_REG_UNPROTECT);
}

en_result_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig);
en_result_t INTC_IrqSignOut(IRQn_Type enIRQn);
en_result_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState);
void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState);
void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState);

en_result_t NMI_Init(const stc_nmi_init_t *pstcNmiInit);
en_result_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit);
en_flag_status_t NMI_GetNmiStatus(uint32_t u32Flag);
void NMI_ClearNmiStatus(uint32_t u32Flag);

en_result_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit);
en_result_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit);
en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32Ch);
void EXTINT_ClearExtIntStatus(uint32_t u32Ch);

void INTC_EKeyCmd(uint8_t u8EKey, en_functional_state_t enNewState);

void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void IRQ000_Handler(void);
void IRQ001_Handler(void);
void IRQ002_Handler(void);
void IRQ003_Handler(void);
void IRQ004_Handler(void);
void IRQ005_Handler(void);
void IRQ006_Handler(void);
void IRQ007_Handler(void);
void IRQ008_Handler(void);
void IRQ009_Handler(void);
void IRQ010_Handler(void);
void IRQ011_Handler(void);
void IRQ012_Handler(void);
void IRQ013_Handler(void);
void IRQ014_Handler(void);
void IRQ015_Handler(void);
void IRQ016_Handler(void);
void IRQ017_Handler(void);
void IRQ018_Handler(void);
void IRQ019_Handler(void);
void IRQ020_Handler(void);
void IRQ021_Handler(void);
void IRQ022_Handler(void);
void IRQ023_Handler(void);
void IRQ024_Handler(void);
void IRQ025_Handler(void);
void IRQ026_Handler(void);
void IRQ027_Handler(void);
void IRQ028_Handler(void);
void IRQ029_Handler(void);
void IRQ030_Handler(void);
void IRQ031_Handler(void);

void NMI_IrqHandler(void);
void HardFault_IrqHandler(void);
void SVC_IrqHandler(void);
void PendSV_IrqHandler(void);
void SysTick_IrqHandler(void);

void EXTINT00_IrqHandler(void);
void EXTINT01_IrqHandler(void);
void EXTINT02_IrqHandler(void);
void EXTINT03_IrqHandler(void);
void EXTINT04_IrqHandler(void);
void EXTINT05_IrqHandler(void);
void EXTINT06_IrqHandler(void);
void EXTINT07_IrqHandler(void);
void EXTINT08_IrqHandler(void);
void EXTINT09_IrqHandler(void);
void EXTINT10_IrqHandler(void);
void EXTINT11_IrqHandler(void);

void DMA_TC0_IrqHandler(void);
void DMA_BTC0_IrqHandler(void);
void DMA_TC1_IrqHandler(void);
void DMA_BTC1_IrqHandler(void);
void DMA_Error_IrqHandler(void);

void EFM_ProgramEraseError_IrqHandler(void);
void EFM_ColError_IrqHandler(void);
void EFM_OpEnd_IrqHandler(void);

void CLK_XtalStop_IrqHandler(void);

void SWDT_IrqHandler(void);

void TMRB_1_Ovf_IrqHandler(void);
void TMRB_1_Udf_IrqHandler(void);
void TMRB_1_Cmp_IrqHandler(void);
void TMRB_2_Ovf_IrqHandler(void);
void TMRB_2_Udf_IrqHandler(void);
void TMRB_2_Cmp_IrqHandler(void);
void TMRB_3_Ovf_IrqHandler(void);
void TMRB_3_Udf_IrqHandler(void);
void TMRB_3_Cmp_IrqHandler(void);
void TMRB_4_Ovf_IrqHandler(void);
void TMRB_4_Udf_IrqHandler(void);
void TMRB_4_Cmp_IrqHandler(void);
void TMRB_5_Ovf_IrqHandler(void);
void TMRB_5_Udf_IrqHandler(void);
void TMRB_5_Cmp_IrqHandler(void);
void TMRB_6_Ovf_IrqHandler(void);
void TMRB_6_Udf_IrqHandler(void);
void TMRB_6_Cmp_IrqHandler(void);
void TMRB_7_Ovf_IrqHandler(void);
void TMRB_7_Udf_IrqHandler(void);
void TMRB_7_Cmp_IrqHandler(void);
void TMRB_8_Ovf_IrqHandler(void);
void TMRB_8_Udf_IrqHandler(void);
void TMRB_8_Cmp_IrqHandler(void);

void USART1_RxError_IrqHandler(void);
void USART1_RxEnd_IrqHandler(void);
void USART1_TxEmpty_IrqHandler(void);
void USART1_TxEnd_IrqHandler(void);
void USART2_RxError_IrqHandler(void);
void USART2_RxEnd_IrqHandler(void);
void USART2_TxEmpty_IrqHandler(void);
void USART2_TxEnd_IrqHandler(void);
void USART3_RxError_IrqHandler(void);
void USART3_RxEnd_IrqHandler(void);
void USART3_TxEmpty_IrqHandler(void);
void USART3_TxEnd_IrqHandler(void);
void USART4_RxError_IrqHandler(void);
void USART4_RxEnd_IrqHandler(void);
void USART4_TxEmpty_IrqHandler(void);
void USART4_TxEnd_IrqHandler(void);
void USART5_RxError_IrqHandler(void);
void USART5_RxEnd_IrqHandler(void);
void USART5_TxEmpty_IrqHandler(void);
void USART5_TxEnd_IrqHandler(void);
void USART6_RxError_IrqHandler(void);
void USART6_RxEnd_IrqHandler(void);
void USART6_TxEmpty_IrqHandler(void);
void USART6_TxEnd_IrqHandler(void);

void I2C_RxEnd_IrqHandler(void);
void I2C_TxEmpty_IrqHandler(void);
void I2C_TxEnd_IrqHandler(void);
void I2C_EE_IrqHandler(void);

void SPI_RxEnd_IrqHandler(void);
void SPI_TxEmpty_IrqHandler(void);
void SPI_Idle_IrqHandler(void);
void SPI_Error_IrqHandler(void);

void CTC_IrqHandler(void);

void EKEY_IrqHandler(void);

void TMR0_CmpA_IrqHandler(void);

void ADC_SeqA_IrqHandler(void);
void ADC_SeqB_IrqHandler(void);
void ADC_Cmp0_IrqHandler(void);
void ADC_Cmp1_IrqHandler(void);

void PWC_LVD_IrqHandler(void);

void RTC_Alarm_IrqHandler(void);
void RTC_Period_IrqHandler(void);

/**
 * @}
 */

#endif /* DDL_INTERRUPTS_ENABLE */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __HC32F160_INTERRUPTS_H__ */

/*******************************************************************************
 * EOF (not truncated)
 ******************************************************************************/
